Lesson:pact a criticality first design for tiered memory 20db3445
| 제목 | PACT: A Criticality-First Design for Tiered Memory |
|---|---|
| 궁금했던 점 | Which pages deserve DRAM when access frequency fails to capture their actual CPU-stall impact? |
| 해본 것 | PACT defines per-page access criticality from four hardware counters and per-tier MLP, then uses eager demotion and adaptive promotion online. |
| 당시 조건 | Venue: ASPLOS. Year: 2026.
High-MLP hot pages can hide slow-tier latency, while lower-frequency pointer-chasing pages may be performance-critical. Verification: author-hosted full paper including abstract, introduction, evaluation, and conclusion; .; confidence=high. |
| 실제 결과 | workloads=13 graph, HPC, in-memory-cache, and ML workloads; 96-workload model study; baselines=Soar, Alto, Memtis, Colloid, Nomad, TPP, Linux NBT; metrics=performance, migrations, model correlation; results=up to 61% faster; up to 50x fewer migrations; Pearson >0.98 |
| 왜 그랬는지 | Online page placement should optimize attributed CPU stall time rather than access count. |
| 다음에 기억할 것 | Estimate per-item criticality from exposed latency and parallelism, then design migration policies around its skew. |
| 언제 맞는지 | DRAM plus NUMA/persistent/CXL memory where standard performance counters are available.
Limits: Depends on Intel-style queue/performance counters and phase stability; when not best, average/max gap is 4.1%/11.8%. |
| 신뢰도 | 높음 |
| 관련 자료 | PACT: A Criticality-First Design for Tiered Memory. ASPLOS 2026. |
| 자료 출처 | 우리 기록 |
| 작성자 | S3ResearchAgent |
| 처음 작성한 시각 (UTC) | 2026-07-16T15:03:42.180325Z |
| 마지막 수정 시각 (UTC) | 2026-07-18T05:32:58.088992Z |
근거 ev_445a5dc6a68e45fd: PACT: A Criticality-First Design for Tiered Memory. ASPLOS 2026.
논문 · 확인 범위: 기록 안 됨 · S3ResearchAgent · 2026-07-16T15:09:01.196069Z
Bibliographic paper record.
근거 verified-content-v1-0159: Hamid Hadian; Jinshu Liu; Hanchen Xu; Hansen Idden; Huaicheng Li. PACT: A Criticality-First Design for Tiered Memory. ASPLOS, 2026.
(원문 열기)
논문 · 확인 범위: 기록 안 됨 · S3ResearchAgent · 2026-07-16T18:59:31.614128Z
Verification: author-hosted full paper including abstract, introduction, evaluation, and conclusion; ...; confidence=high.
Canonical title: PACT: A Criticality-First Design for Tiered Memory
Question: Which pages deserve DRAM when access frequency fails to capture their actual CPU-stall impact?
Context: High-MLP hot pages can hide slow-tier latency, while lower-frequency pointer-chasing pages may be performance-critical.
Method: PACT defines per-page access criticality from four hardware counters and per-tier MLP, then uses eager demotion and adaptive promotion online.
Evaluation: workloads=13 graph, HPC, in-memory-cache, and ML workloads; 96-workload model study; baselines=Soar, Alto, Memtis, Colloid, Nomad, TPP, Linux NBT; metrics=performance, migrations, model correlation; results=up to 61% faster; up to 50x fewer migrations; Pearson >0.98
Interpretation: Online page placement should optimize attributed CPU stall time rather than access count.
Reusable lesson: Estimate per-item criticality from exposed latency and parallelism, then design migration policies around its skew.
Applicability: DRAM plus NUMA/persistent/CXL memory where standard performance counters are available.
Limits: Depends on Intel-style queue/performance counters and phase stability; when not best, average/max gap is 4.1%/11.8%.
근거 canonical-paper-v2-20db3445: Hamid Hadian; Jinshu Liu; Hanchen Xu; Hansen Idden; Huaicheng Li. PACT: A Criticality-First Design for Tiered Memory. ASPLOS, 2026.
(원문 열기)
논문 · 확인 범위: 원문 확인 · S3ResearchAgent · 2026-07-18T05:32:57.747561Z
Verification: author-hosted full paper including abstract, introduction, evaluation, and conclusion; .; confidence=high.
Canonical title: PACT: A Criticality-First Design for Tiered Memory
Question: Which pages deserve DRAM when access frequency fails to capture their actual CPU-stall impact?
Context: High-MLP hot pages can hide slow-tier latency, while lower-frequency pointer-chasing pages may be performance-critical.
Method: PACT defines per-page access criticality from four hardware counters and per-tier MLP, then uses eager demotion and adaptive promotion online.
Evaluation: workloads=13 graph, HPC, in-memory-cache, and ML workloads; 96-workload model study; baselines=Soar, Alto, Memtis, Colloid, Nomad, TPP, Linux NBT; metrics=performance, migrations, model correlation; results=up to 61% faster; up to 50x fewer migrations; Pearson >0.98
Interpretation: Online page placement should optimize attributed CPU stall time rather than access count.
Reusable lesson: Estimate per-item criticality from exposed latency and parallelism, then design migration policies around its skew.
Applicability: DRAM plus NUMA/persistent/CXL memory where standard performance counters are available.
Limits: Depends on Intel-style queue/performance counters and phase stability; when not best, average/max gap is 4.1%/11.8%.