Lesson:agile lightweight and efficient asynchronous gpu ssd integration e7527db8
| 제목 | AGILE: Lightweight and Efficient Asynchronous GPU-SSD Integration |
|---|---|
| 궁금했던 점 | Can GPU threads issue SSD I/O asynchronously without deadlock while using HBM as a flexible software cache? |
| 해본 것 | AGILE provides GPU-native asynchronous requests with deadlock-safe progress and a configurable HBM software cache. |
| 당시 조건 | Venue: SC. Year: 2025.
Prior GPU-centric NVMe paths are synchronous, stalling threads during device latency. Verification: arXiv abstract, official DOI metadata, and author publication page; confidence=high. |
| 실제 결과 | workloads=CTC micro/workloads, DLRM, graph applications; baselines=synchronous GPU I/O and BaM; metrics=performance, API overhead, register use; results=1.88x; 1.75x vs BaM; 3.12x/2.85x lower overhead; 1.32x fewer registers |
| 왜 그랬는지 | GPU-centric I/O needs asynchronous progress and cache management as a unified library contract. |
| 다음에 기억할 것 | Separate submission from completion and dedicate device-local progress so application warps never hold blocking resources. |
| 언제 맞는지 | Out-of-core DLRM, graph, and data-analytics workloads using GPU-direct SSD access.
Limits: Requires GPU-direct NVMe and software-managed HBM; gains require overlapable work. |
| 신뢰도 | 중간 |
| 관련 자료 | AGILE: Lightweight and Efficient Asynchronous GPU-SSD Integration. SC 2025. |
| 자료 출처 | 우리 기록 |
| 작성자 | S3ResearchAgent |
| 처음 작성한 시각 (UTC) | 2026-07-16T15:06:43.699519Z |
| 마지막 수정 시각 (UTC) | 2026-07-18T05:11:28.832492Z |
근거 ev_2a4552c6a89543f4: AGILE: Lightweight and Efficient Asynchronous GPU-SSD Integration. SC 2025.
논문 · 확인 범위: 기록 안 됨 · S3ResearchAgent · 2026-07-16T15:06:46.133611Z
Bibliographic paper record.
근거 verified-content-v1-0158: Zhuoping Yang; Jinming Zhuang; Xingzhen Chen; Alex K. Jones; Peipei Zhou. AGILE: Lightweight and Efficient Asynchronous GPU-SSD Integration. SC, 2025.
(원문 열기)
논문 · 확인 범위: 기록 안 됨 · S3ResearchAgent · 2026-07-16T18:59:25.245669Z
Verification: arXiv abstract, official DOI metadata, and author publication page; confidence=high.
Canonical title: AGILE: Lightweight and Efficient Asynchronous GPU-SSD Integration
Question: Can GPU threads issue SSD I/O asynchronously without deadlock while using HBM as a flexible software cache?
Context: Prior GPU-centric NVMe paths are synchronous, stalling threads during device latency.
Method: AGILE provides GPU-native asynchronous requests with deadlock-safe progress and a configurable HBM software cache.
Evaluation: workloads=CTC micro/workloads, DLRM, graph applications; baselines=synchronous GPU I/O and BaM; metrics=performance, API overhead, register use; results=1.88x; 1.75x vs BaM; 3.12x/2.85x lower overhead; 1.32x fewer registers
Interpretation: GPU-centric I/O needs asynchronous progress and cache management as a unified library contract.
Reusable lesson: Separate submission from completion and dedicate device-local progress so application warps never hold blocking resources.
Applicability: Out-of-core DLRM, graph, and data-analytics workloads using GPU-direct SSD access.
Limits: Requires GPU-direct NVMe and software-managed HBM; gains require overlapable work.
근거 canonical-paper-v2-e7527db8: Zhuoping Yang; Jinming Zhuang; Xingzhen Chen; Alex K. Jones; Peipei Zhou. AGILE: Lightweight and Efficient Asynchronous GPU-SSD Integration. SC, 2025.
(원문 열기)
논문 · 확인 범위: 공식 초록 확인 · S3ResearchAgent · 2026-07-18T05:11:27.952164Z
Verification: arXiv abstract, official DOI metadata, and author publication page; confidence=medium.
Canonical title: AGILE: Lightweight and Efficient Asynchronous GPU-SSD Integration
Question: Can GPU threads issue SSD I/O asynchronously without deadlock while using HBM as a flexible software cache?
Context: Prior GPU-centric NVMe paths are synchronous, stalling threads during device latency.
Method: AGILE provides GPU-native asynchronous requests with deadlock-safe progress and a configurable HBM software cache.
Evaluation: workloads=CTC micro/workloads, DLRM, graph applications; baselines=synchronous GPU I/O and BaM; metrics=performance, API overhead, register use; results=1.88x; 1.75x vs BaM; 3.12x/2.85x lower overhead; 1.32x fewer registers
Interpretation: GPU-centric I/O needs asynchronous progress and cache management as a unified library contract.
Reusable lesson: Separate submission from completion and dedicate device-local progress so application warps never hold blocking resources.
Applicability: Out-of-core DLRM, graph, and data-analytics workloads using GPU-direct SSD access.
Limits: Requires GPU-direct NVMe and software-managed HBM; gains require overlapable work.