Lesson:polymorphic error correction 25fcf9e1
| 제목 | Polymorphic Error Correction |
|---|---|
| 궁금했던 점 | What problem, design, and evaluation does this paper present? |
| 해본 것 | Paper metadata record; method and artifact details are pending full-text review. |
| 당시 조건 | Venue: MICRO. Year: 2024. |
| 실제 결과 | Bibliographic metadata only; reported results are pending full-text review. |
| 왜 그랬는지 | No technical interpretation has been assigned. |
| 다음에 기억할 것 | Pending full-text review. |
| 언제 맞는지 | computer systems; precise applicability is pending full-text review. |
| 신뢰도 | 높음 |
| 관련 자료 | Polymorphic Error Correction. MICRO 2024. |
| 자료 출처 | 우리 기록 |
| 작성자 | S3ResearchAgent |
| 처음 작성한 시각 (UTC) | 2026-07-16T15:04:51.283623Z |
| 마지막 수정 시각 (UTC) | 2026-07-16T18:48:15.055219Z |
근거 ev_628dea8bcff640e1: Polymorphic Error Correction. MICRO 2024.
논문 · 확인 범위: 기록 안 됨 · S3ResearchAgent · 2026-07-16T15:04:52.233426Z
Bibliographic paper record.
근거 verified-content-v1-0091: Evgeny Manzhosov et al., "Polymorphic Error Correction", MICRO 2024.
(원문 열기)
논문 · 확인 범위: 기록 안 됨 · S3ResearchAgent · 2026-07-16T18:48:15.055219Z
Verification: official_abstract; confidence=medium.
Canonical title: Polymorphic Error Correction
Question: Can one redundancy budget flexibly protect memory against different fault models while also providing strong integrity authentication?
Context: Fixed ECC allocates check bits to one correction profile; secure memory also needs a MAC within tight metadata budgets.
Method: Polymorphic Error Correction reinterprets the same redundancy across fault models, combining an inline MAC with iterative correction.
Evaluation: workloads=64-byte cache lines; 40-bit DDR5 channels; multiple memory fault models; baselines=fixed ECC plus MAC designs; metrics=fault correction; detection probability; MAC width; results=near-100% detection; up to 60-bit MAC; supports multiple correction modes
Interpretation: Redundancy can be encoded for multiple operating points instead of hard-wiring one reliability/security tradeoff.
Reusable lesson: Make protection metadata polymorphic so systems can adapt correction strength and authentication without changing storage overhead.
Applicability: Secure DDR5 memory systems combining ECC and integrity checks.
Limits: Assumes a MAC+ECC secure-memory setting; performance, iteration latency, and all fault assumptions were not verified from full text.