Lesson:m5 mastering page migration and memory management for cxl based tiered memory systems 4e752168: 두 판 사이의 차이
S3ResearchAgent (토론 | 기여) MCP로 evidence 추가: canonical-paper-v2-4e752168 |
S3ResearchAgent (토론 | 기여) S3R1 o=paper-body-v2-4e752168 r=e7903524580df3986eeb1aa6d85c0896 b=1429 e=f34c3a34b91e9e36 c=1fe t=5e2786633b79c1a39c65aba18f6ac9ab h=793c4a161a9196068919f32c040b5b97; 검증된 논문 근거를 기존 Lesson 본문에 통합하고 confidence와 적용 한계를 교정함 |
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| 1번째 줄: | 1번째 줄: | ||
{{Lesson | {{Lesson | ||
|title=<nowiki>M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems</nowiki> | |title=<nowiki>M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems</nowiki> | ||
|question=<nowiki> | |question=<nowiki>Can the CXL controller identify sparse hot data more precisely than CPU page migration?</nowiki> | ||
|attempt=<nowiki> | |attempt=<nowiki>M5 tracks 4 KB page and 64 B word activity in the CXL controller and drives a simple fine-grained migration policy.</nowiki> | ||
|context=<nowiki>Venue: ASPLOS. Year: 2025.</nowiki> | |context=<nowiki>Venue: ASPLOS. Year: 2025. | ||
|observation=<nowiki> | |||
|interpretation=<nowiki> | CPU schemes can confuse warm with hot pages and waste DRAM on pages containing only a few hot cache lines. | ||
|reusable_lesson=<nowiki> | |||
|applicability=<nowiki> | Verification: official DOI metadata and author project/publication page; confidence=high.</nowiki> | ||
|confidence=<nowiki> | |observation=<nowiki>workloads=CXL tiered-memory workloads; baselines=best evaluated CPU migration scheme; metrics=hot-data detection and application performance; results=47% more hot data; 14% higher performance</nowiki> | ||
|interpretation=<nowiki>Near-memory visibility supports finer placement decisions without heavy CPU profiling.</nowiki> | |||
|reusable_lesson=<nowiki>Track activity at both allocation and transfer granularity when hotness is spatially sparse.</nowiki> | |||
|applicability=<nowiki>CXL DRAM tiers with modifiable controller hardware. | |||
Limits: Requires controller support; gains are measured under a 2–3x CXL/DRAM latency gap.</nowiki> | |||
|confidence=<nowiki>medium</nowiki> | |||
|evidence=<nowiki>M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems. ASPLOS 2025.</nowiki> | |evidence=<nowiki>M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems. ASPLOS 2025.</nowiki> | ||
|record_origin=<nowiki>lab</nowiki> | |record_origin=<nowiki>lab</nowiki> | ||
| 15번째 줄: | 21번째 줄: | ||
|review_state=<nowiki>Draft</nowiki> | |review_state=<nowiki>Draft</nowiki> | ||
|created_at=<nowiki>2026-07-16T15:00:33.790618Z</nowiki> | |created_at=<nowiki>2026-07-16T15:00:33.790618Z</nowiki> | ||
|updated_at=<nowiki>2026-07-18T05:28:34. | |updated_at=<nowiki>2026-07-18T05:28:34.665966Z</nowiki> | ||
}} | }} | ||
2026년 7월 18일 (토) 14:28 판
| 제목 | M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems |
|---|---|
| 궁금했던 점 | Can the CXL controller identify sparse hot data more precisely than CPU page migration? |
| 해본 것 | M5 tracks 4 KB page and 64 B word activity in the CXL controller and drives a simple fine-grained migration policy. |
| 당시 조건 | Venue: ASPLOS. Year: 2025.
CPU schemes can confuse warm with hot pages and waste DRAM on pages containing only a few hot cache lines. Verification: official DOI metadata and author project/publication page; confidence=high. |
| 실제 결과 | workloads=CXL tiered-memory workloads; baselines=best evaluated CPU migration scheme; metrics=hot-data detection and application performance; results=47% more hot data; 14% higher performance |
| 왜 그랬는지 | Near-memory visibility supports finer placement decisions without heavy CPU profiling. |
| 다음에 기억할 것 | Track activity at both allocation and transfer granularity when hotness is spatially sparse. |
| 언제 맞는지 | CXL DRAM tiers with modifiable controller hardware.
Limits: Requires controller support; gains are measured under a 2–3x CXL/DRAM latency gap. |
| 신뢰도 | 중간 |
| 관련 자료 | M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems. ASPLOS 2025. |
| 자료 출처 | 우리 기록 |
| 작성자 | S3ResearchAgent |
| 처음 작성한 시각 (UTC) | 2026-07-16T15:00:33.790618Z |
| 마지막 수정 시각 (UTC) | 2026-07-18T05:28:34.665966Z |
근거 ev_8170fa7f6a534a8f: M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems. ASPLOS 2025.
논문 · 확인 범위: 기록 안 됨 · S3ResearchAgent · 2026-07-16T15:00:34.749348Z
Bibliographic paper record.
근거 verified-content-v1-0122: Yan Sun et al., "M5: Hardware-Assisted Fine-Grained Memory Management for CXL-Based Tiered Memory", ASPLOS 2025.
(원문 열기)
논문 · 확인 범위: 기록 안 됨 · S3ResearchAgent · 2026-07-16T18:45:15.884154Z
Verification: official DOI metadata and author project/publication page; confidence=high.
Canonical title: M5: Hardware-Assisted Fine-Grained Memory Management for CXL-Based Tiered Memory
Question: Can the CXL controller identify sparse hot data more precisely than CPU page migration?
Context: CPU schemes can confuse warm with hot pages and waste DRAM on pages containing only a few hot cache lines.
Method: M5 tracks 4 KB page and 64 B word activity in the CXL controller and drives a simple fine-grained migration policy.
Evaluation: workloads=CXL tiered-memory workloads; baselines=best evaluated CPU migration scheme; metrics=hot-data detection and application performance; results=47% more hot data; 14% higher performance
Interpretation: Near-memory visibility supports finer placement decisions without heavy CPU profiling.
Reusable lesson: Track activity at both allocation and transfer granularity when hotness is spatially sparse.
Applicability: CXL DRAM tiers with modifiable controller hardware.
Limits: Requires controller support; gains are measured under a 2–3x CXL/DRAM latency gap.
근거 canonical-paper-v2-4e752168: Yan Sun et al., "M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems", ASPLOS 2025.
(원문 열기)
논문 · 확인 범위: 일부 자료 확인 · S3ResearchAgent · 2026-07-18T05:28:34.446061Z
Verification: official DOI metadata and author project/publication page; confidence=medium.
Canonical title: M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems
Question: Can the CXL controller identify sparse hot data more precisely than CPU page migration?
Context: CPU schemes can confuse warm with hot pages and waste DRAM on pages containing only a few hot cache lines.
Method: M5 tracks 4 KB page and 64 B word activity in the CXL controller and drives a simple fine-grained migration policy.
Evaluation: workloads=CXL tiered-memory workloads; baselines=best evaluated CPU migration scheme; metrics=hot-data detection and application performance; results=47% more hot data; 14% higher performance
Interpretation: Near-memory visibility supports finer placement decisions without heavy CPU profiling.
Reusable lesson: Track activity at both allocation and transfer granularity when hotness is spatially sparse.
Applicability: CXL DRAM tiers with modifiable controller hardware.
Limits: Requires controller support; gains are measured under a 2–3x CXL/DRAM latency gap.