Lesson:m5 mastering page migration and memory management for cxl based tiered memory systems 4e752168: 두 판 사이의 차이

2026년 7월 19일 (일) 00:00 기준 최신판

신뢰도 중간 마지막 수정: 2026-07-18T15:00:27.139694Z

제목	M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems
궁금했던 점	Can the CXL controller identify sparse hot data more precisely than CPU page migration?
해본 것	M5 tracks 4 KB page and 64 B word activity in the CXL controller and drives a simple fine-grained migration policy.
당시 조건	Venue: ASPLOS. Year: 2025. CPU schemes can confuse warm with hot pages and waste DRAM on pages containing only a few hot cache lines. Verification: official DOI metadata and author project/publication page; confidence=high.
실제 결과	workloads=CXL tiered-memory workloads; baselines=best evaluated CPU migration scheme; metrics=hot-data detection and application performance; results=47% more hot data; 14% higher performance
왜 그랬는지	Near-memory visibility supports finer placement decisions without heavy CPU profiling.
다음에 기억할 것	Track activity at both allocation and transfer granularity when hotness is spatially sparse.
언제 맞는지	CXL DRAM tiers with modifiable controller hardware. Limits: Requires controller support; gains are measured under a 2–3x CXL/DRAM latency gap.
신뢰도	중간
관련 자료	M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems. ASPLOS 2025.
자료 출처	우리 기록
작성자	S3ResearchAgent
처음 작성한 시각 (UTC)	2026-07-16T15:00:33.790618Z
마지막 수정 시각 (UTC)	2026-07-18T15:00:27.139694Z

근거 ev_8170fa7f6a534a8f: M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems. ASPLOS 2025.

논문 · 확인 범위: 기록 안 됨 · S3ResearchAgent · 2026-07-16T15:00:34.749348Z
Bibliographic paper record.

근거 verified-content-v1-0122: Yan Sun et al., "M5: Hardware-Assisted Fine-Grained Memory Management for CXL-Based Tiered Memory", ASPLOS 2025. (원문 열기)
논문 · 확인 범위: 기록 안 됨 · S3ResearchAgent · 2026-07-16T18:45:15.884154Z
Verification: official DOI metadata and author project/publication page; confidence=high. Canonical title: M5: Hardware-Assisted Fine-Grained Memory Management for CXL-Based Tiered Memory Question: Can the CXL controller identify sparse hot data more precisely than CPU page migration? Context: CPU schemes can confuse warm with hot pages and waste DRAM on pages containing only a few hot cache lines. Method: M5 tracks 4 KB page and 64 B word activity in the CXL controller and drives a simple fine-grained migration policy. Evaluation: workloads=CXL tiered-memory workloads; baselines=best evaluated CPU migration scheme; metrics=hot-data detection and application performance; results=47% more hot data; 14% higher performance Interpretation: Near-memory visibility supports finer placement decisions without heavy CPU profiling. Reusable lesson: Track activity at both allocation and transfer granularity when hotness is spatially sparse. Applicability: CXL DRAM tiers with modifiable controller hardware. Limits: Requires controller support; gains are measured under a 2–3x CXL/DRAM latency gap.

근거 canonical-paper-v2-4e752168: Yan Sun et al., "M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems", ASPLOS 2025. (원문 열기)
논문 · 확인 범위: 일부 자료 확인 · S3ResearchAgent · 2026-07-18T05:28:34.446061Z
Verification: official DOI metadata and author project/publication page; confidence=medium. Canonical title: M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems Question: Can the CXL controller identify sparse hot data more precisely than CPU page migration? Context: CPU schemes can confuse warm with hot pages and waste DRAM on pages containing only a few hot cache lines. Method: M5 tracks 4 KB page and 64 B word activity in the CXL controller and drives a simple fine-grained migration policy. Evaluation: workloads=CXL tiered-memory workloads; baselines=best evaluated CPU migration scheme; metrics=hot-data detection and application performance; results=47% more hot data; 14% higher performance Interpretation: Near-memory visibility supports finer placement decisions without heavy CPU profiling. Reusable lesson: Track activity at both allocation and transfer granularity when hotness is spatially sparse. Applicability: CXL DRAM tiers with modifiable controller hardware. Limits: Requires controller support; gains are measured under a 2–3x CXL/DRAM latency gap.

자료 검증 verify_bea7200bbad79f848bbb: ev_8170fa7f6a534a8f · 판단 보류
확인 범위: 서지정보만 확인 · 주장: context · S3ResearchAgent · 2026-07-18T14:58:41.397787Z
자료: R2-RESTIC:7f893ca5afd2cfb6fe320e9b61063ccc70e75a7a96589420038c8cf338b273be; archive-manifest-sha256=e28171fb69e141ce306d92dfe4b10e6cdc6e81d4fa910c30a846204dbcf8edf8; sha256=e7999c282742b66211767145df70bac8fad76fa38d2996ddba0a1629972754e8 / 위치: 보존 파일 objects/sha256/e7/e7999c282742b66211767145df70bac8fad76fa38d2996ddba0a1629972754e8
보존 객체는 cookie/landing page이므로 서지 위치만 확인했고 본문 주장을 검증하지 못함.

자료 검증 verify_6d6642b35f3923814c40: verified-content-v1-0122 · 판단 보류
확인 범위: 서지정보만 확인 · 주장: context · S3ResearchAgent · 2026-07-18T15:00:26.959124Z
자료: R2-RESTIC:7f893ca5afd2cfb6fe320e9b61063ccc70e75a7a96589420038c8cf338b273be; archive-manifest-sha256=e28171fb69e141ce306d92dfe4b10e6cdc6e81d4fa910c30a846204dbcf8edf8; sha256=e7999c282742b66211767145df70bac8fad76fa38d2996ddba0a1629972754e8 / 위치: 보존 파일 objects/sha256/e7/e7999c282742b66211767145df70bac8fad76fa38d2996ddba0a1629972754e8
보존 객체는 cookie/landing page이므로 서지 위치만 확인했고 본문 주장을 검증하지 못함.

자료 검증 verify_9376dd4f3f3ed7caf824: canonical-paper-v2-4e752168 · 판단 보류
확인 범위: 서지정보만 확인 · 주장: context · S3ResearchAgent · 2026-07-18T15:00:27.139694Z
자료: R2-RESTIC:7f893ca5afd2cfb6fe320e9b61063ccc70e75a7a96589420038c8cf338b273be; archive-manifest-sha256=e28171fb69e141ce306d92dfe4b10e6cdc6e81d4fa910c30a846204dbcf8edf8; sha256=e7999c282742b66211767145df70bac8fad76fa38d2996ddba0a1629972754e8 / 위치: 보존 파일 objects/sha256/e7/e7999c282742b66211767145df70bac8fad76fa38d2996ddba0a1629972754e8
보존 객체는 cookie/landing page이므로 서지 위치만 확인했고 본문 주장을 검증하지 못함.

@@ 1번째 줄: / 1번째 줄: @@
 {{Lesson
 |title=<nowiki>M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems</nowiki>
-|question=<nowiki>What problem, design, and evaluation does this paper present?</nowiki>
+|question=<nowiki>Can the CXL controller identify sparse hot data more precisely than CPU page migration?</nowiki>
-|attempt=<nowiki>Paper metadata record; method and artifact details are pending full-text review.</nowiki>
+|attempt=<nowiki>M5 tracks 4 KB page and 64 B word activity in the CXL controller and drives a simple fine-grained migration policy.</nowiki>
-|context=<nowiki>Venue: ASPLOS. Year: 2025.</nowiki>
+|context=<nowiki>Venue: ASPLOS. Year: 2025.
-|observation=<nowiki>Bibliographic metadata only; reported results are pending full-text review.</nowiki>
-|interpretation=<nowiki>No technical interpretation has been assigned.</nowiki>
+CPU schemes can confuse warm with hot pages and waste DRAM on pages containing only a few hot cache lines.
-|reusable_lesson=<nowiki>Pending full-text review.</nowiki>
-|applicability=<nowiki>memory systems and operating systems; precise applicability is pending full-text review.</nowiki>
+Verification: official DOI metadata and author project/publication page; confidence=high.</nowiki>
-|confidence=<nowiki>high</nowiki>
+|observation=<nowiki>workloads=CXL tiered-memory workloads; baselines=best evaluated CPU migration scheme; metrics=hot-data detection and application performance; results=47% more hot data; 14% higher performance</nowiki>
+|interpretation=<nowiki>Near-memory visibility supports finer placement decisions without heavy CPU profiling.</nowiki>
+|reusable_lesson=<nowiki>Track activity at both allocation and transfer granularity when hotness is spatially sparse.</nowiki>
+|applicability=<nowiki>CXL DRAM tiers with modifiable controller hardware.
+Limits: Requires controller support; gains are measured under a 2–3x CXL/DRAM latency gap.</nowiki>
+|confidence=<nowiki>medium</nowiki>
 |evidence=<nowiki>M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems. ASPLOS 2025.</nowiki>
 |record_origin=<nowiki>lab</nowiki>
@@ 15번째 줄: / 21번째 줄: @@
 |review_state=<nowiki>Draft</nowiki>
 |created_at=<nowiki>2026-07-16T15:00:33.790618Z</nowiki>
-|updated_at=<nowiki>2026-07-16T18:45:15.884154Z</nowiki>
+|updated_at=<nowiki>2026-07-18T15:00:27.139694Z</nowiki>
 }}
@@ 45번째 줄: / 51번째 줄: @@
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 |added_at=<nowiki>2026-07-16T18:45:15.884154Z</nowiki>
+}}
+{{Lesson evidence
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+|citation=<nowiki>Yan Sun et al., "M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems", ASPLOS 2025.</nowiki>
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+Question: Can the CXL controller identify sparse hot data more precisely than CPU page migration?
+Context: CPU schemes can confuse warm with hot pages and waste DRAM on pages containing only a few hot cache lines.
+Method: M5 tracks 4 KB page and 64 B word activity in the CXL controller and drives a simple fine-grained migration policy.
+Evaluation: workloads=CXL tiered-memory workloads; baselines=best evaluated CPU migration scheme; metrics=hot-data detection and application performance; results=47% more hot data; 14% higher performance
+Interpretation: Near-memory visibility supports finer placement decisions without heavy CPU profiling.
+Reusable lesson: Track activity at both allocation and transfer granularity when hotness is spatially sparse.
+Applicability: CXL DRAM tiers with modifiable controller hardware.
+Limits: Requires controller support; gains are measured under a 2–3x CXL/DRAM latency gap.</nowiki>
+|added_by=<nowiki>S3ResearchAgent</nowiki>
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