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속성:Evidence note

S3 연구 메모리

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자료에서 확인할 수 있는 점이나 한계를 적습니다.

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towards efficient flash caches with emerging nvme flexible data placement ssds 8683a6eb +
Bibliographic paper record.  +
towards efficient flash caches with emerging nvme flexible data placement ssds 8683a6eb +
Verification: arXiv paper/abstract and official DOI metadata; confidence=high. Canonical title: Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs Question: Can flash caches reduce internal garbage collection and write amplification by exposing data lifetime? Context: Mixed-lifetime cache objects cause NAND garbage collection to copy still-live data during reclamation. Method: The work integrates NVMe Flexible Data Placement into CacheLib and segregates writes by expected lifetime. Evaluation: workloads=Meta/Twitter production cache traces; baselines=conventional flash-cache placement; metrics=device write amplification, garbage collection, overhead; results=write amplification approximately 1 with little overhead Interpretation: Host-known object lifetime is sufficient to make flash placement substantially more efficient. Reusable lesson: Pass lifecycle hints across the host/device boundary instead of forcing the FTL to infer them. Applicability: Large flash caches on FDP-capable SSDs with classifiable object lifetimes. Limits: Requires FDP support and useful lifetime classification; results reflect production cache configurations.  +
translation pass through for near native paging performance in vms c096bffc +
Verification: abstract_only; confidence=high. Canonical title: Translation Pass-Through for Near-Native Paging Performance in VMs Question: VM의 중첩 페이지 변환 비용을 격리를 유지하며 제거할 수 있는가? Context: 2차원 페이지 워크는 TLB miss와 메모리 관리 작업을 크게 느리게 한다. Method: TPT는 게스트가 1차원 GVA→HPA 페이지 표를 제어하고 물리 메모리 태그로 호스트 격리를 보장한다. Evaluation: workloads=datacenter applications; KVM/QEMU on x86; baselines=nested paging; shadow paging; native; metrics=runtime; paging performance; results=Up to 2.4× vs nested and 1.4× vs shadow paging. Interpretation: 하드웨어 태깅이 있으면 번역 권한을 게스트에 넘기면서 격리를 유지할 수 있다. Reusable lesson: 가상화 간접 계층은 검증 가능한 하드웨어 태그로 축소할 수 있다. Applicability: 메모리 집약 VM과 데이터센터 가상화. Limits: AMD 태그 메커니즘을 에뮬레이션했고 게스트 OS 수정이 필요하다.  +
translation pass through for near native paging performance in vms c096bffc +
Verification: abstract_only; confidence=medium. Canonical title: Translation Pass-Through for Near-Native Paging Performance in VMs Question: VM의 중첩 페이지 변환 비용을 격리를 유지하며 제거할 수 있는가? Context: 2차원 페이지 워크는 TLB miss와 메모리 관리 작업을 크게 느리게 한다. Method: TPT는 게스트가 1차원 GVA→HPA 페이지 표를 제어하고 물리 메모리 태그로 호스트 격리를 보장한다. Evaluation: workloads=datacenter applications; KVM/QEMU on x86; baselines=nested paging; shadow paging; native; metrics=runtime; paging performance; results=Up to 2.4× vs nested and 1.4× vs shadow paging. Interpretation: 하드웨어 태깅이 있으면 번역 권한을 게스트에 넘기면서 격리를 유지할 수 있다. Reusable lesson: 가상화 간접 계층은 검증 가능한 하드웨어 태그로 축소할 수 있다. Applicability: 메모리 집약 VM과 데이터센터 가상화. Limits: AMD 태그 메커니즘을 에뮬레이션했고 게스트 OS 수정이 필요하다.  +
translation pass through for near native paging performance in vms c096bffc +
Bibliographic paper record.  +
transparent and selective real time interrupt services for performance improvement 6b173779 +
Source: Yonsei University Computer Systems Laboratory publication list supplied by the user. Manifestation 1 of 1.  +
transparent and selective real time interrupt services for performance improvement 6b173779 +
정본 Lesson 보강 근거. 검토 원본: Lesson:technical_review_transparent_and_selective_real_time_interrupt_services_for_performance_improvem_b78f264b. 확인 범위: official_abstract. 확인한 자료: https://doi.org/10.1007/978-3-540-75664-4_28 ; https://yonsei.elsevierpure.com/en/publications/transparent-and-selective-real-time-interrupt-services-for-perfor/ ; https://opendl.ifip-tc6.org/db/conf/seus/seus2007/index.html. 질문, 방법, 평가, 해석, 재사용 교훈, 적용 범위와 한계를 같은 Lesson 본문에 통합했습니다.  +
transparent smartphone memory expansion 5ad5fd6a +
Source: Yonsei University Computer Systems Laboratory publication list supplied by the user. Manifestation 1 of 1.  +
transparent smartphone memory expansion 5ad5fd6a +
정본 Lesson 보강 근거. 검토 원본: Lesson:technical_review_transparent_smartphone_memory_expansion_f1adb2b8. 확인 범위: official_abstract. 확인한 자료: https://yonsei.elsevierpure.com/en/publications/transparent-smartphone-memory-expansion/ ; https://doi.org/10.1145/3672608.3707936 ; https://web.comp.polyu.edu.hk/sac25msc/accept.html. 질문, 방법, 평가, 해석, 재사용 교훈, 적용 범위와 한계를 같은 Lesson 본문에 통합했습니다.  +
transparently bridging semantic gap in cpu management for virtualized environments 2485a772 +
Source: Yonsei University Computer Systems Laboratory publication list supplied by the user. Manifestation 1 of 1.  +
transparently bridging semantic gap in cpu management for virtualized environments 2485a772 +
정본 Lesson 보강 근거. 검토 원본: Lesson:technical_review_transparently_bridging_semantic_gap_in_cpu_management_for_virtualized_environme_ddf55f9b. 확인 범위: official_abstract. 확인한 자료: https://doi.org/10.1016/j.jpdc.2010.11.005 ; https://www.sciencedirect.com/science/article/abs/pii/S0743731510002376 ; https://yonsei.elsevierpure.com/en/publications/transparently-bridging-semantic-gap-in-cpu-management-for-virtual/. 질문, 방법, 평가, 해석, 재사용 교훈, 적용 범위와 한계를 같은 Lesson 본문에 통합했습니다.  +
transparently exploiting device reserved memory for application performance in mobile systems 43e55454 +
정본 Lesson 보강 근거. 검토 원본: Lesson:technical_review_transparently_exploiting_device_reserved_memory_for_application_performance_in_d2f8d46b. 확인 범위: official_abstract. 확인한 자료: https://doi.org/10.1109/TMC.2015.2504934 ; https://yonsei.elsevierpure.com/en/publications/transparently-exploiting-device-reserved-memory-for-application-p/. 질문, 방법, 평가, 해석, 재사용 교훈, 적용 범위와 한계를 같은 Lesson 본문에 통합했습니다.  +
transparently exploiting device reserved memory for application performance in mobile systems 43e55454 +
Source: Yonsei University Computer Systems Laboratory publication list supplied by the user. Manifestation 1 of 1.  +
twinpilots a new computing paradigm for gpu cpu parallel llm inference aa39d085 +
Bibliographic paper record.  +
twinpilots a new computing paradigm for gpu cpu parallel llm inference aa39d085 +
Verification: official_abstract; confidence=medium. Canonical title: TwinPilots: A New Computing Paradigm for GPU-CPU Parallel LLM Inference Question: Can CPU and GPU execute different LLM operators concurrently when the model exceeds GPU memory? Context: Conventional offloading serializes transfer and GPU work, leaving CPU compute underused. Method: TwinPilots schedules asymmetric CPU/GPU multiprocessing, balances operator work, and hides data transfer behind CPU execution. Evaluation: workloads=OPT/Llama 13B, 30B, 33B; NVIDIA A10G 24 GB; AMD EPYC 7R32 256 GB; baselines=state-of-the-art CPU-offload schemes; metrics=throughput; data-transfer cost; results=up to 3.39x throughput; 72.1% lower transfer cost Interpretation: CPU computation can be a first-class parallel lane rather than only a staging mechanism for GPU offload. Reusable lesson: Overlap heterogeneous compute and movement by assigning complementary operators to each processor. Applicability: Single-server LLM inference with GPU-memory-constrained models. Limits: Evidence is tied to one CPU/GPU server and selected models; gains depend on operator balance and host memory bandwidth.  +
twinpilots a new computing paradigm for gpu cpu parallel llm inference aa39d085 +
Verification: official_abstract; confidence=high. Canonical title: TwinPilots: A New Computing Paradigm for GPU-CPU Parallel LLM Inference Question: Can CPU and GPU execute different LLM operators concurrently when the model exceeds GPU memory? Context: Conventional offloading serializes transfer and GPU work, leaving CPU compute underused. Method: TwinPilots schedules asymmetric CPU/GPU multiprocessing, balances operator work, and hides data transfer behind CPU execution. Evaluation: workloads=OPT/Llama 13B, 30B, 33B; NVIDIA A10G 24 GB; AMD EPYC 7R32 256 GB; baselines=state-of-the-art CPU-offload schemes; metrics=throughput; data-transfer cost; results=up to 3.39x throughput; 72.1% lower transfer cost Interpretation: CPU computation can be a first-class parallel lane rather than only a staging mechanism for GPU offload. Reusable lesson: Overlap heterogeneous compute and movement by assigning complementary operators to each processor. Applicability: Single-server LLM inference with GPU-memory-constrained models. Limits: Evidence is tied to one CPU/GPU server and selected models; gains depend on operator balance and host memory bandwidth.  +
twob a two tier web browser architecture optimized for mobile network 1b67a324 +
정본 Lesson 보강 근거. 검토 원본: Lesson:technical_review_twob_a_two_tier_web_browser_architecture_optimized_for_mobile_network_448d8064. 확인 범위: official_abstract. 확인한 자료: https://doi.org/10.1145/2428955.2429006 ; https://yonsei.elsevierpure.com/en/publications/twob-a-two-tier-web-browser-architecture-optimized-for-mobile-net/. 질문, 방법, 평가, 해석, 재사용 교훈, 적용 범위와 한계를 같은 Lesson 본문에 통합했습니다.  +
twob a two tier web browser architecture optimized for mobile network 1b67a324 +
Source: Yonsei University Computer Systems Laboratory publication list supplied by the user. Manifestation 1 of 1.  +
u
ufs bbe26b78 +
정본 Lesson 보강 근거. 검토 원본: Lesson:technical_review_ufs_a8ea798b. 확인 범위: partial_source. 세부 범위: official_abstract_partial. 확인한 자료: https://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE12318615 ; https://cslab.yonsei.ac.kr/publications. 질문, 방법, 평가, 해석, 재사용 교훈, 적용 범위와 한계를 같은 Lesson 본문에 통합했습니다.  +
ufs bbe26b78 +
Imported from the lab publication list.  +
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