속성:Evidence note
자료에서 확인할 수 있는 점이나 한계를 적습니다.
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Verification: abstract_only; confidence=high.
Canonical title: UGACHE: A Unified GPU Cache for Embedding-based Deep Learning
Question: 다중 GPU에서 임베딩 캐시의 복제와 분할 한계를 동시에 피할 수 있는가?
Context: 임베딩 접근은 읽기 전용·배치·편향·예측 가능하지만 GPU 간 링크 혼잡이 크다.
Method: factored extraction과 hotness·토폴로지 기반 근최적 배치로 로컬/원격 접근을 균형화한다.
Evaluation: workloads=GNN training; DL recommendation inference; TensorFlow; PyTorch; baselines=replication design; partition design; metrics=training/inference performance; results=Average 1.93×/1.63×, up to 5.25×/3.45× vs replication/partition.
Interpretation: 캐시 용량뿐 아니라 GPU 간 추출 경로의 대역폭을 최적화해야 한다.
Reusable lesson: 다중 가속기 캐시는 hotness와 인터커넥트 토폴로지를 함께 모델링하라.
Applicability: GNN 학습과 추천 임베딩 추론.
Limits: 읽기 전용·편향·예측 가능한 임베딩 접근과 단일 노드 다중 GPU를 전제한다. +
Verification: abstract_only; confidence=medium.
Canonical title: UGACHE: A Unified GPU Cache for Embedding-based Deep Learning
Question: 다중 GPU에서 임베딩 캐시의 복제와 분할 한계를 동시에 피할 수 있는가?
Context: 임베딩 접근은 읽기 전용·배치·편향·예측 가능하지만 GPU 간 링크 혼잡이 크다.
Method: factored extraction과 hotness·토폴로지 기반 근최적 배치로 로컬/원격 접근을 균형화한다.
Evaluation: workloads=GNN training; DL recommendation inference; TensorFlow; PyTorch; baselines=replication design; partition design; metrics=training/inference performance; results=Average 1.93×/1.63×, up to 5.25×/3.45× vs replication/partition.
Interpretation: 캐시 용량뿐 아니라 GPU 간 추출 경로의 대역폭을 최적화해야 한다.
Reusable lesson: 다중 가속기 캐시는 hotness와 인터커넥트 토폴로지를 함께 모델링하라.
Applicability: GNN 학습과 추천 임베딩 추론.
Limits: 읽기 전용·편향·예측 가능한 임베딩 접근과 단일 노드 다중 GPU를 전제한다. +
Bibliographic paper record. +
understanding and mitigating covert and side channel vulnerabilities introduced by rowhammer def 0e272653 +
Verification: latest arXiv abstract/full text and official MICRO program; confidence=high.
Canonical title: Understanding and Mitigating Covert Channel and Side Channel Vulnerabilities Introduced by RowHammer Defenses
Question: Do RowHammer defenses themselves create exploitable timing channels?
Context: Defense-induced refresh, throttling, or tracking alters memory timing in ways visible across protection boundaries.
Method: LeakyHammer constructs covert/side channels from defense behavior, demonstrates website fingerprinting, and evaluates three mitigations.
Evaluation: workloads=two constructed channels and website-fingerprinting attack; baselines=RowHammer defenses with and without three mitigations; metrics=channel bandwidth, attack success, mitigation overhead; results=41.9 and 54.0 Kbps in latest version
Interpretation: A defense can close an integrity attack while opening an information-flow channel through its observable actions.
Reusable lesson: Evaluate security mechanisms for timing/noninterference, not only for prevention efficacy.
Applicability: DRAM systems deploying stateful or throttling-based RowHammer defenses.
Limits: Channel feasibility and mitigation overhead depend on the specific defense and platform; arXiv versions report different older rates. +
understanding and mitigating covert and side channel vulnerabilities introduced by rowhammer def 0e272653 +
Verification: latest arXiv abstract/full text and official MICRO program; confidence=high.
Canonical title: Understanding and Mitigating Covert Channel and Side Channel Vulnerabilities Introduced by RowHammer Defenses
Question: Do RowHammer defenses themselves create exploitable timing channels?
Context: Defense-induced refresh, throttling, or tracking alters memory timing in ways visible across protection boundaries.
Method: LeakyHammer constructs covert/side channels from defense behavior, demonstrates website fingerprinting, and evaluates three mitigations.
Evaluation: workloads=two constructed channels and website-fingerprinting attack; baselines=RowHammer defenses with and without three mitigations; metrics=channel bandwidth, attack success, mitigation overhead; results=41.9 and 54.0 Kbps in latest version
Interpretation: A defense can close an integrity attack while opening an information-flow channel through its observable actions.
Reusable lesson: Evaluate security mechanisms for timing/noninterference, not only for prevention efficacy.
Applicability: DRAM systems deploying stateful or throttling-based RowHammer defenses.
Limits: Channel feasibility and mitigation overhead depend on the specific defense and platform; arXiv versions report different older rates. +
understanding and mitigating covert and side channel vulnerabilities introduced by rowhammer def 0e272653 +
Bibliographic paper record. +
Verification: official_abstract; confidence=high.
Canonical title: Understanding Silent Data Corruptions in a Large Production CPU Population
Question: What do processor silent data corruptions look like in production, and how do vulnerable features, reproducibility, and environmental triggers affect mitigation?
Context: Traditional tests miss silent computation errors, leaving little field evidence for fault models or fleet policy.
Method: The study analyzes SDCs across more than one million production processors, tests reproducibility and triggers such as temperature, and derives mitigation implications.
Evaluation: workloads=production population of over one million processors; baselines=existing production CPU testing practices; metrics=SDC incidence; reproducibility; feature vulnerability; trigger conditions; results=field taxonomy over >1M CPUs; no numeric fleet rate stated in accessible primary abstract
Interpretation: SDC policy must distinguish stable, testable faults from intermittent environment-dependent faults.
Reusable lesson: Build reliability controls from field-derived fault classes and trigger conditions, not a single synthetic fault rate.
Applicability: Hyperscale CPU qualification, fleet monitoring, and SDC mitigation.
Limits: Production data and CPU population are provider-specific; sensitive rates and all sampling biases are not exposed in the abstract. +
Verification: official_abstract; confidence=medium.
Canonical title: Understanding Silent Data Corruptions in a Large Production CPU Population
Question: What do processor silent data corruptions look like in production, and how do vulnerable features, reproducibility, and environmental triggers affect mitigation?
Context: Traditional tests miss silent computation errors, leaving little field evidence for fault models or fleet policy.
Method: The study analyzes SDCs across more than one million production processors, tests reproducibility and triggers such as temperature, and derives mitigation implications.
Evaluation: workloads=production population of over one million processors; baselines=existing production CPU testing practices; metrics=SDC incidence; reproducibility; feature vulnerability; trigger conditions; results=field taxonomy over >1M CPUs; no numeric fleet rate stated in accessible primary abstract
Interpretation: SDC policy must distinguish stable, testable faults from intermittent environment-dependent faults.
Reusable lesson: Build reliability controls from field-derived fault classes and trigger conditions, not a single synthetic fault rate.
Applicability: Hyperscale CPU qualification, fleet monitoring, and SDC mitigation.
Limits: Production data and CPU population are provider-specific; sensitive rates and all sampling biases are not exposed in the abstract. +
Bibliographic paper record. +
Verification: abstract_only; confidence=high.
Canonical title: UnFaaSener: Latency and Cost Aware Offloading of Functions from Serverless Platforms
Question: 유휴 외부 자원을 활용해 FaaS 비용을 줄이면서 지연 목표를 지킬 수 있는가?
Context: VM·온프레미스·개인 호스트의 잉여 자원은 남지만 서버리스 호출은 계속 과금된다.
Method: pub/sub 기반 비동기 스케줄러가 가용성·비용·지연·DAG QoS에 따라 함수 일부를 오프로딩한다.
Evaluation: workloads=function DAGs on heterogeneous harvested hosts; baselines=cloud-only FaaS; metrics=cost; latency/QoS; results=Up to 89.8% cost saving at a 90% resource cap.
Interpretation: 함수 단위 선택 오프로딩은 이질적 잉여 자원을 안전한 보조 계층으로 만든다.
Reusable lesson: 비용 최적화는 전부 이전보다 함수별·QoS별 부분 이전이 현실적이다.
Applicability: 하이브리드·멀티클라우드 서버리스.
Limits: 신뢰 가능한 잉여 컴퓨트, pub/sub, 지연·가용성 예측이 필요하다. +
Verification: abstract_only; confidence=medium.
Canonical title: UnFaaSener: Latency and Cost Aware Offloading of Functions from Serverless Platforms
Question: 유휴 외부 자원을 활용해 FaaS 비용을 줄이면서 지연 목표를 지킬 수 있는가?
Context: VM·온프레미스·개인 호스트의 잉여 자원은 남지만 서버리스 호출은 계속 과금된다.
Method: pub/sub 기반 비동기 스케줄러가 가용성·비용·지연·DAG QoS에 따라 함수 일부를 오프로딩한다.
Evaluation: workloads=function DAGs on heterogeneous harvested hosts; baselines=cloud-only FaaS; metrics=cost; latency/QoS; results=Up to 89.8% cost saving at a 90% resource cap.
Interpretation: 함수 단위 선택 오프로딩은 이질적 잉여 자원을 안전한 보조 계층으로 만든다.
Reusable lesson: 비용 최적화는 전부 이전보다 함수별·QoS별 부분 이전이 현실적이다.
Applicability: 하이브리드·멀티클라우드 서버리스.
Limits: 신뢰 가능한 잉여 컴퓨트, pub/sub, 지연·가용성 예측이 필요하다. +
Bibliographic paper record. +
unicom a universally high performant i o completion mechanism for modern computer systems 9172fe3e +
Verification: official USENIX page and paper PDF/abstract; confidence=high.
Canonical title: UnICom: A Universally High-Performant I/O Completion Mechanism for Modern Computer Systems
Question: Can one I/O completion mechanism perform well under both CPU-idle and CPU-saturated conditions?
Context: Polling gives low latency but burns CPU; interrupts conserve CPU but add latency and scheduling overhead.
Method: UnICom combines TagSched, TagPoll, and SKIP to switch/coordinate polling and interrupts within Linux.
Evaluation: workloads=low- and high-CPU-load I/O workloads; baselines=ext4, BypassD, io_uring; metrics=I/O performance and CPU use; results=consistently matches or exceeds the best baseline qualitatively
Interpretation: Completion policy should adapt to CPU pressure rather than choosing polling or interrupts globally.
Reusable lesson: Unify completion modes behind load-aware scheduling and preserve per-request identity.
Applicability: Modern Linux storage across variable CPU utilization.
Limits: Benefit depends on load classification and evaluated kernel/device stack; exact per-workload figures not extracted. +
unicom a universally high performant i o completion mechanism for modern computer systems 9172fe3e +
Verification: official USENIX page and paper PDF/abstract; confidence=high.
Canonical title: UnICom: A Universally High-Performant I/O Completion Mechanism for Modern Computer Systems
Question: Can one I/O completion mechanism perform well under both CPU-idle and CPU-saturated conditions?
Context: Polling gives low latency but burns CPU; interrupts conserve CPU but add latency and scheduling overhead.
Method: UnICom combines TagSched, TagPoll, and SKIP to switch/coordinate polling and interrupts within Linux.
Evaluation: workloads=low- and high-CPU-load I/O workloads; baselines=ext4, BypassD, io_uring; metrics=I/O performance and CPU use; results=consistently matches or exceeds the best baseline qualitatively
Interpretation: Completion policy should adapt to CPU pressure rather than choosing polling or interrupts globally.
Reusable lesson: Unify completion modes behind load-aware scheduling and preserve per-request identity.
Applicability: Modern Linux storage across variable CPU utilization.
Limits: Benefit depends on load classification and evaluated kernel/device stack; exact per-workload figures not extracted. +
unicom a universally high performant i o completion mechanism for modern computer systems 9172fe3e +
Bibliographic paper record. +
Bibliographic paper record. +
Verification: official_abstract; confidence=high.
Question: How can cache-coherent disaggregated memory avoid extra address translation, cache pollution, and migration amplification?
Context: Conventional local-cache/remote-memory layering adds translation and can waste local capacity on poorly chosen data.
Method: UniMem unifies local and remote memory, redesigns the local cache, and migrates data using hotness and hotness-fragmentation signals.
Evaluation: workloads=disaggregated-memory workloads; names not stated in abstract; baselines=state-of-the-art disaggregated-memory designs; names not stated; metrics=average memory-access time; data amplification; results=up to 76.4% lower average memory-access time
Interpretation: A unified hierarchy can remove redundant lookup paths while making local capacity and migration more selective.
Reusable lesson: Treat cache placement, translation, and migration as one hierarchy-wide policy.
Applicability: Cache-coherent disaggregated-memory systems.
Limits: The accessible official abstract does not name every workload or comparator; benefits depend on coherence and topology. +
Verification: official_abstract; confidence=medium.
Question: How can cache-coherent disaggregated memory avoid extra address translation, cache pollution, and migration amplification?
Context: Conventional local-cache/remote-memory layering adds translation and can waste local capacity on poorly chosen data.
Method: UniMem unifies local and remote memory, redesigns the local cache, and migrates data using hotness and hotness-fragmentation signals.
Evaluation: workloads=disaggregated-memory workloads; names not stated in abstract; baselines=state-of-the-art disaggregated-memory designs; names not stated; metrics=average memory-access time; data amplification; results=up to 76.4% lower average memory-access time
Interpretation: A unified hierarchy can remove redundant lookup paths while making local capacity and migration more selective.
Reusable lesson: Treat cache placement, translation, and migration as one hierarchy-wide policy.
Applicability: Cache-coherent disaggregated-memory systems.
Limits: The accessible official abstract does not name every workload or comparator; benefits depend on coherence and topology. +
Verification: official_abstract; confidence=high.
Canonical title: USHER: Holistic Interference Avoidance for Resource Optimized ML Inference
Question: How can GPU inference services spatially multiplex models while meeting latency SLOs and avoiding cache/compute/memory interference?
Context: Naive colocation raises utilization but unpredictable inter-model interference lowers goodput and cost efficiency.
Method: USHER combines GPU-kernel resource estimation, an interference-aware scheduler for batch size/replication/placement, and operator-graph merging to reduce cache interference.
Evaluation: workloads=large-scale production ML inference workloads; baselines=existing GPU inference multiplexing methods; metrics=goodput; cost efficiency; latency-SLO compliance; scale; results=up to 2.6x goodput; up to 3.5x cost efficiency; scales to thousands of GPUs
Interpretation: Resource estimation, placement, and graph-level execution must be coordinated to make GPU multiplexing economical.
Reusable lesson: Model interference explicitly and optimize configuration and execution structure together.
Applicability: Large multi-model GPU inference fleets with latency SLOs.
Limits: Estimator and heuristic accuracy depend on model/operator mix, workload stationarity, GPU architecture, and SLOs. +
Bibliographic paper record. +