속성:Evidence note
자료에서 확인할 수 있는 점이나 한계를 적습니다.
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Verification: abstract_only; confidence=medium.
Canonical title: Overcoming the Memory Wall with CXL-Enabled SSDs
Question: SSD를 CXL 메모리 확장 장치처럼 사용하면서 지연과 수명을 감당할 수 있는가?
Context: DRAM 확장은 비싸고 플래시는 느리며 쓰기 수명 제한이 있다.
Method: CXL 인터페이스와 SSD 내부 캐싱·prefetch를 공동 설계한다.
Evaluation: workloads=real-world memory traces; baselines=conventional SSD/memory expansion designs; metrics=access latency; estimated lifetime; results=68–91% of requests under 1 μs; estimated lifetime ≥3.1 years.
Interpretation: 대부분의 접근을 캐시·예측으로 흡수하면 플래시를 메모리 계층에 넣을 여지가 있다.
Reusable lesson: 느린 매체를 메모리화할 때 지연 분포와 endurance를 동시에 평가하라.
Applicability: CXL 메모리 확장과 대용량 메모리 워크로드.
Limits: 일부 결과가 추정·프로토타입 기반이며 플래시 수명과 tail에 민감하다. +
Bibliographic paper record. +
Verification: abstract_only; confidence=high.
Canonical title: Overcoming the Memory Wall with CXL-Enabled SSDs
Question: SSD를 CXL 메모리 확장 장치처럼 사용하면서 지연과 수명을 감당할 수 있는가?
Context: DRAM 확장은 비싸고 플래시는 느리며 쓰기 수명 제한이 있다.
Method: CXL 인터페이스와 SSD 내부 캐싱·prefetch를 공동 설계한다.
Evaluation: workloads=real-world memory traces; baselines=conventional SSD/memory expansion designs; metrics=access latency; estimated lifetime; results=68–91% of requests under 1 μs; estimated lifetime ≥3.1 years.
Interpretation: 대부분의 접근을 캐시·예측으로 흡수하면 플래시를 메모리 계층에 넣을 여지가 있다.
Reusable lesson: 느린 매체를 메모리화할 때 지연 분포와 endurance를 동시에 평가하라.
Applicability: CXL 메모리 확장과 대용량 메모리 워크로드.
Limits: 일부 결과가 추정·프로토타입 기반이며 플래시 수명과 tail에 민감하다. +
ozz identifying kernel out of order concurrency bugs with in vivo memory access reordering 0b85f639 +
Verification: official_abstract; confidence=medium.
Canonical title: OZZ: Identifying Kernel Out-of-Order Concurrency Bugs with In-Vivo Memory Access Reordering
Question: How can tests deterministically expose kernel bugs caused jointly by weak-memory reordering and thread interleavings?
Context: Incorrect memory-barrier use creates rare concurrency failures that ordinary schedules and hardware execution reproduce unreliably.
Method: OEMU emulates processor memory-access reordering during live kernel execution; Ozz jointly controls reorderings and thread interleavings for systematic testing.
Evaluation: workloads=previously reported Linux OoO bugs; latest Linux kernel; baselines=native nondeterministic execution; metrics=bug reproduction; new confirmed bugs; results=reproduced known bugs; 11 new developer-confirmed and patched bugs
Interpretation: Making weak-memory effects controllable turns a probabilistic hardware behavior into a testable schedule dimension.
Reusable lesson: Emulate nondeterministic low-level behavior and explore it jointly with software scheduling.
Applicability: Linux kernel concurrency testing, memory-barrier validation, and fuzzing.
Limits: Emulation coverage is bounded by the modeled memory behavior and explored schedules; findings focus on Linux. +
ozz identifying kernel out of order concurrency bugs with in vivo memory access reordering 0b85f639 +
Bibliographic paper record. +
ozz identifying kernel out of order concurrency bugs with in vivo memory access reordering 0b85f639 +
Verification: official_abstract; confidence=high.
Canonical title: OZZ: Identifying Kernel Out-of-Order Concurrency Bugs with In-Vivo Memory Access Reordering
Question: How can tests deterministically expose kernel bugs caused jointly by weak-memory reordering and thread interleavings?
Context: Incorrect memory-barrier use creates rare concurrency failures that ordinary schedules and hardware execution reproduce unreliably.
Method: OEMU emulates processor memory-access reordering during live kernel execution; Ozz jointly controls reorderings and thread interleavings for systematic testing.
Evaluation: workloads=previously reported Linux OoO bugs; latest Linux kernel; baselines=native nondeterministic execution; metrics=bug reproduction; new confirmed bugs; results=reproduced known bugs; 11 new developer-confirmed and patched bugs
Interpretation: Making weak-memory effects controllable turns a probabilistic hardware behavior into a testable schedule dimension.
Reusable lesson: Emulate nondeterministic low-level behavior and explore it jointly with software scheduling.
Applicability: Linux kernel concurrency testing, memory-barrier validation, and fuzzing.
Limits: Emulation coverage is bounded by the modeled memory behavior and explored schedules; findings focus on Linux. +
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Verification: official DOI/EuroSys metadata and author project full-text summary; confidence=medium.
Canonical title: PaCaR: Improved Buffered I/O Locality on NUMA Systems with Page Cache Replication
Question: Can NUMA systems replicate page-cache data to restore locality without breaking buffered-I/O consistency?
Context: A single page-cache copy can force remote NUMA accesses for file-heavy multithreaded workloads.
Method: PaCaR maintains a main page plus per-node twins, invalidates replicas, switches the main copy, and integrates replication with PFRA/LRU in Linux 6.12.
Evaluation: workloads=Filebench, fio, RocksDB on dual-NUMA Intel Xeon; baselines=Linux 6.12 page cache; metrics=throughput/performance and write overhead; results=up to 40% Filebench and 8% RocksDB improvement; minimal write overhead
Interpretation: Read-mostly page-cache replication can trade controlled coherence for substantial NUMA locality.
Reusable lesson: Replicate shared read-heavy kernel data at NUMA boundaries and make ownership transitions explicit.
Applicability: Multi-socket NUMA servers running buffered file I/O.
Limits: Current implementation does not support mmap; write-heavy benefits are constrained by invalidation/coherence. +
Bibliographic paper record. +
Verification: official DOI/EuroSys metadata and author project full-text summary; confidence=high.
Canonical title: PaCaR: Improved Buffered I/O Locality on NUMA Systems with Page Cache Replication
Question: Can NUMA systems replicate page-cache data to restore locality without breaking buffered-I/O consistency?
Context: A single page-cache copy can force remote NUMA accesses for file-heavy multithreaded workloads.
Method: PaCaR maintains a main page plus per-node twins, invalidates replicas, switches the main copy, and integrates replication with PFRA/LRU in Linux 6.12.
Evaluation: workloads=Filebench, fio, RocksDB on dual-NUMA Intel Xeon; baselines=Linux 6.12 page cache; metrics=throughput/performance and write overhead; results=up to 40% Filebench and 8% RocksDB improvement; minimal write overhead
Interpretation: Read-mostly page-cache replication can trade controlled coherence for substantial NUMA locality.
Reusable lesson: Replicate shared read-heavy kernel data at NUMA boundaries and make ownership transitions explicit.
Applicability: Multi-socket NUMA servers running buffered file I/O.
Limits: Current implementation does not support mmap; write-heavy benefits are constrained by invalidation/coherence. +
Bibliographic paper record. +
Verification: author-hosted full paper including abstract, introduction, evaluation, and conclusion; .; confidence=high.
Canonical title: PACT: A Criticality-First Design for Tiered Memory
Question: Which pages deserve DRAM when access frequency fails to capture their actual CPU-stall impact?
Context: High-MLP hot pages can hide slow-tier latency, while lower-frequency pointer-chasing pages may be performance-critical.
Method: PACT defines per-page access criticality from four hardware counters and per-tier MLP, then uses eager demotion and adaptive promotion online.
Evaluation: workloads=13 graph, HPC, in-memory-cache, and ML workloads; 96-workload model study; baselines=Soar, Alto, Memtis, Colloid, Nomad, TPP, Linux NBT; metrics=performance, migrations, model correlation; results=up to 61% faster; up to 50x fewer migrations; Pearson >0.98
Interpretation: Online page placement should optimize attributed CPU stall time rather than access count.
Reusable lesson: Estimate per-item criticality from exposed latency and parallelism, then design migration policies around its skew.
Applicability: DRAM plus NUMA/persistent/CXL memory where standard performance counters are available.
Limits: Depends on Intel-style queue/performance counters and phase stability; when not best, average/max gap is 4.1%/11.8%. +
Verification: author-hosted full paper including abstract, introduction, evaluation, and conclusion; ...; confidence=high.
Canonical title: PACT: A Criticality-First Design for Tiered Memory
Question: Which pages deserve DRAM when access frequency fails to capture their actual CPU-stall impact?
Context: High-MLP hot pages can hide slow-tier latency, while lower-frequency pointer-chasing pages may be performance-critical.
Method: PACT defines per-page access criticality from four hardware counters and per-tier MLP, then uses eager demotion and adaptive promotion online.
Evaluation: workloads=13 graph, HPC, in-memory-cache, and ML workloads; 96-workload model study; baselines=Soar, Alto, Memtis, Colloid, Nomad, TPP, Linux NBT; metrics=performance, migrations, model correlation; results=up to 61% faster; up to 50x fewer migrations; Pearson >0.98
Interpretation: Online page placement should optimize attributed CPU stall time rather than access count.
Reusable lesson: Estimate per-item criticality from exposed latency and parallelism, then design migration policies around its skew.
Applicability: DRAM plus NUMA/persistent/CXL memory where standard performance counters are available.
Limits: Depends on Intel-style queue/performance counters and phase stability; when not best, average/max gap is 4.1%/11.8%. +
Bibliographic paper record. +
Verification: abstract_only; confidence=medium.
Canonical title: Paella: Low-latency Model Serving with Software-defined GPU Scheduling
Question: GPU 모델 서빙에서 블랙박스 하드웨어 스케줄링을 우회해 꼬리 지연을 줄일 수 있는가?
Context: 동시 모델의 커널 순서를 GPU가 불투명하게 결정해 SLO 제어가 어렵다.
Method: 컴파일러·클라이언트·스케줄러를 공동 설계해 소프트웨어가 커널 순서와 정책을 정한다.
Evaluation: workloads=8-model serving mix; two extreme models; baselines=hardware-scheduled serving baseline; metrics=latency; throughput; fairness; results=Lower latency and higher pre-saturation throughput; exact aggregate not abstract-verified.
Interpretation: 모델 단위가 아니라 GPU 커널 단위 제어가 지연 격리의 핵심이다.
Reusable lesson: 가속기 스케줄링 정책을 런타임이 명시적으로 제어하게 하라.
Applicability: 다중 테넌트 GPU 추론.
Limits: 컴파일러·런타임 통합과 하드웨어별 커널 제어가 필요하며 정확한 수치는 초록에서 검증되지 않았다. +
Verification: abstract_only; confidence=medium.
Canonical title: Paella: Low-latency Model Serving with Software-defined GPU Scheduling
Question: GPU 모델 서빙에서 블랙박스 하드웨어 스케줄링을 우회해 꼬리 지연을 줄일 수 있는가?
Context: 동시 모델의 커널 순서를 GPU가 불투명하게 결정해 SLO 제어가 어렵다.
Method: 컴파일러·클라이언트·스케줄러를 공동 설계해 소프트웨어가 커널 순서와 정책을 정한다.
Evaluation: workloads=8-model serving mix; two extreme models; baselines=hardware-scheduled serving baseline; metrics=latency; throughput; fairness; results=Lower latency and higher pre-saturation throughput; exact aggregate not abstract-verified.
Interpretation: 모델 단위가 아니라 GPU 커널 단위 제어가 지연 격리의 핵심이다.
Reusable lesson: 가속기 스케줄링 정책을 런타임이 명시적으로 제어하게 하라.
Applicability: 다중 테넌트 GPU 추론.
Limits: 컴파일러·런타임 통합과 하드웨어별 커널 제어가 필요하며 정확한 수치는 초록에서 검증되지 않았다. +
papi exploiting dynamic parallelism in large language model decoding with a processing in memory 5f9f53cc +
Verification: official DOI metadata and arXiv abstract; confidence=medium.
Canonical title: PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System
Question: How should heterogeneous GPU and PIM resources be scheduled as LLM kernels alternate between compute- and memory-bound phases?
Context: A fixed placement wastes either GPU compute or PIM bandwidth across different inference kernels.
Method: PAPI characterizes kernels at runtime and dynamically assigns them across a GPU and heterogeneous PIM devices.
Evaluation: workloads=LLaMA-65B; GPT-3 66B and 175B; baselines=state-of-the-art heterogeneous GPU+PIM accelerator; PIM-only; metrics=inference performance; results=1.8x and 11.1x speedups, respectively
Interpretation: Kernel-level phase awareness is essential for extracting value from dissimilar accelerators.
Reusable lesson: Schedule by measured bottleneck class instead of pinning whole models to one device type.
Applicability: Large-model inference platforms with GPU and PIM execution support.
Limits: Benefits depend on specialized PIM hardware and the evaluated model/kernel mix. +
papi exploiting dynamic parallelism in large language model decoding with a processing in memory 5f9f53cc +
Verification: official DOI metadata and arXiv abstract; confidence=high.
Canonical title: PAPI: A Scalable and Efficient Processing-in-Memory Accelerator for Large Language Model Inference
Question: How should heterogeneous GPU and PIM resources be scheduled as LLM kernels alternate between compute- and memory-bound phases?
Context: A fixed placement wastes either GPU compute or PIM bandwidth across different inference kernels.
Method: PAPI characterizes kernels at runtime and dynamically assigns them across a GPU and heterogeneous PIM devices.
Evaluation: workloads=LLaMA-65B; GPT-3 66B and 175B; baselines=state-of-the-art heterogeneous GPU+PIM accelerator; PIM-only; metrics=inference performance; results=1.8x and 11.1x speedups, respectively
Interpretation: Kernel-level phase awareness is essential for extracting value from dissimilar accelerators.
Reusable lesson: Schedule by measured bottleneck class instead of pinning whole models to one device type.
Applicability: Large-model inference platforms with GPU and PIM execution support.
Limits: Benefits depend on specialized PIM hardware and the evaluated model/kernel mix. +
papi exploiting dynamic parallelism in large language model decoding with a processing in memory 5f9f53cc +
Bibliographic paper record. +
partial failure resilient memory management system for cxl based distributed shared memory 48948c1d +
Verification: abstract_only; confidence=high.
Canonical title: Partial Failure Resilient Memory Management System for (CXL-based) Distributed Shared Memory
Question: CXL 분산 공유 메모리에서 클라이언트 일부가 죽어도 안전하게 메모리를 회수할 수 있는가?
Context: 클라이언트 장애는 refcount 누수·중복 해제·wild pointer를 만들 수 있다.
Method: CXL-SHM은 era 기반 비차단 reference counting으로 장애 세대와 살아 있는 참조를 구분한다.
Evaluation: workloads=real CXL hardware; microbenchmarks; end-to-end applications; baselines=conventional reference-count management; metrics=safety; allocation/reclamation performance; results=Safety and low overhead verified; exact aggregate not abstract-verified.
Interpretation: 참조를 장애 세대와 결합하면 중앙 정지 없이 죽은 클라이언트의 자원을 회수할 수 있다.
Reusable lesson: 분산 메모리 수명 관리는 프로세스 장애 세대를 참조 메타데이터에 넣어라.
Applicability: CXL 기반 shared-memory pool.
Limits: refcount 순환 참조 가능성과 CXL·부분 장애 모델에 제약된다; 초록에 정량치가 없다. +
partial failure resilient memory management system for cxl based distributed shared memory 48948c1d +
Verification: abstract_only; confidence=medium.
Canonical title: Partial Failure Resilient Memory Management System for (CXL-based) Distributed Shared Memory
Question: CXL 분산 공유 메모리에서 클라이언트 일부가 죽어도 안전하게 메모리를 회수할 수 있는가?
Context: 클라이언트 장애는 refcount 누수·중복 해제·wild pointer를 만들 수 있다.
Method: CXL-SHM은 era 기반 비차단 reference counting으로 장애 세대와 살아 있는 참조를 구분한다.
Evaluation: workloads=real CXL hardware; microbenchmarks; end-to-end applications; baselines=conventional reference-count management; metrics=safety; allocation/reclamation performance; results=Safety and low overhead verified; exact aggregate not abstract-verified.
Interpretation: 참조를 장애 세대와 결합하면 중앙 정지 없이 죽은 클라이언트의 자원을 회수할 수 있다.
Reusable lesson: 분산 메모리 수명 관리는 프로세스 장애 세대를 참조 메타데이터에 넣어라.
Applicability: CXL 기반 shared-memory pool.
Limits: refcount 순환 참조 가능성과 CXL·부분 장애 모델에 제약된다; 초록에 정량치가 없다. +